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MRF89XA
2.15
2.15.1
Interrupt Configuration Registers
FIFO TRANSMIT AND RECEIVE
INTERRUPT REQUEST
CONFIGURATION REGISTER
DETAILS
REGISTER 2-14:
FTXRXIREG: FIFO TRANSMIT AND RECEIVE INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0D) (POR:0x00)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQ0RXS<1:0>
IRQ1RXS<1:0>
IRQ1TX
FIFOFULL
FIFOEMPTY
FOVRRUN
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-6
IRQ0RXS<1:0>: IRQ0 Receive Stand-by bits
These bits control the IRQ0 source in Receive and Stand-by modes:
If DMODE1:DMODE0 = 00
11 = SYNC
10 = SYNC
01 = RSSI
00 = Sync (default)
If DMODE1:DMODE0 = 01
11 = SYNC
10 = FIFOEMPTY (1)
01 = WRITEBYTE
00 = - (default)
If DMODE1:DMODE0 = 1x
Continuous Mode (default)
Buffer Mode
Packet Mode
11 = SYNC or ARDSMATCH (3) (if address filtering is enabled)
10 = FIFOEMPTY (1)
01 = WRITEBYTE
00 = PLREADY (2) (default)
bit 5-4
IRQ1RXS<1:0>: IRQ1 Receive Stand-by bits
These bits control the IRQ1 source in Receive and Stand-by modes:
If DMODE1:DMODE0 = 00
xx = DCLK
If DMODE1:DMODE0 = 01
11 = FIFO_THRESHOLD (1)
10 = RSSI
01 = FIFOFULL (1)
00 = - (default)
If DMODE1:DMODE0 = 1x
Continuous Mode (default)
Buffer Mode
Packet Mode
11 = FIFO_THRESHOLD (1)
10 = RSSI
01 = FIFOFULL (1)
00 = CRCOK (default)
Note 1: This mode is also available in Stand-by mode.
2: PLREADY = Payload ready
3: ADRSMATCH = Address Match
DS70622C-page 38
Preliminary
? 2010–2011 Microchip Technology Inc.
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